S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
16.4.7
Interrupts
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated
flags. Each interrupt is listed and described separately.
16.4.7.1
Description of Interrupt Operation
The MSCAN supports four interrupt vectors (see
Table 16-38),
any of which can be individually masked
(for details see sections from
Section 16.3.2.6, “MSCAN Receiver Interrupt Enable Register
(CANRIER),”
to
Section 16.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”).
The dedicated interrupt vector addresses are defined in the
Resets and
Interrupts
chapter.
Table 16-38. Interrupt Vectors
Interrupt Source
Wake-Up Interrupt (WUPIF)
Error Interrupts Interrupt (CSCIF, OVRIF)
Receive Interrupt (RXF)
Transmit Interrupts (TXE[2:0])
CCR Mask
I bit
I bit
I bit
I bit
Local Enable
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CANTIER (TXEIE[2:0])
16.4.7.2
Transmit Interrupt
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXEx flag of the empty message buffer is set.
16.4.7.3
Receive Interrupt
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO.
This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are
multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the
foreground buffer.
16.4.7.4
Wake-Up Interrupt
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCAN internal sleep mode.
WUPE (see
Section 16.3.2.1, “MSCAN Control Register 0 (CANCTL0)”)
must be enabled.
16.4.7.5
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition
occurrs.
Section 16.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)
indicates one of the following
conditions:
•
Overrun
— An overrun condition of the receiver FIFO as described in
Section 16.4.2.3, “Receive
Structures,”
occurred.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
655
