S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 10 XGATE (S12XGATEV3)
To signal the completion of a task the XGATE is able to send interrupts to the S12X_CPU. Each XGATE
channel has its own interrupt vector. Refer to the
S12X_INT Section
for detailed information.
The XGATE module also provides a set of hardware semaphores which are necessary to ensure data
consistency whenever RAM locations or peripherals are shared with the S12X_CPU.
The following sections describe the components of the XGATE module in further detail.
10.4.1
XGATE RISC Core
The RISC core is a 16 bit processor with an instruction set that is well suited for data transfers, bit
manipulations, and simple arithmetic operations (see
Section 10.8, “Instruction Set”).
It is able to access the MCU’s internal memories and peripherals without blocking these resources from
the S12X_CPU
1
. Whenever the S12X_CPU and the RISC core access the same resource, the RISC core
will be stalled until the resource becomes available again.
1
The XGATE offers a high access rate to the MCU’s internal RAM. Depending on the bus load, the RISC
core can perform up to two RAM accesses per S12X_CPU bus cycle.
Bus accesses to peripheral registers or flash are slower. A transfer rate of one bus access per S12X_CPU
cycle can not be exceeded.
The XGATE module is intended to execute short interrupt service routines that are triggered by peripheral
modules or by software.
10.4.2
Programmer’s Model
Register Block
15
15
15
15
15
15
15
15
Program Counter
0
0
0
0
0
0
0
0
15
R7
(Stack Pointer)
R6
R5
R4
R3
R2
R1
(Data Pointer)
R0 = 0
PC
0
Condition
Code
Register
NZVC
3 2 1 0
Figure 10-22. Programmer’s Model
1. With the exception of PRR registers (see Section “S12X_MMC”).
MC9S12XE-Family Reference Manual , Rev. 1.19
372
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Section
for information on how to select priority levels for XGATE threads. Low priority threads (interrupt
levels 1 to 3) can be interrupted by high priority threads (interrupt levels 4 to 7). High priority threads are
not interruptible. The register content of an interrupted thread is maintained and restored by the XGATE
hardware.
