S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.1.4
Modulus Down-Counter
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used
to latch the values of the IC registers and the pulse accumulators to their holding registers.
The action of latching can be programmed to be periodic or only once.
14.4.1.5
Precision Timer
By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this
case, it is possible to set additional prescaler settings for the main timer counter and modulus down counter
and enhance delay counter settings compared to the settings in the present ECT timer.
14.4.1.6
Flag Clearing Mechanisms
The flags in the ECT can be cleared one of two ways:
1. Normal flag clearing mechanism (TFFCA = 0)
Any of the ECT flags can be cleared by writing a one to the flag.
2. Fast flag clearing mechanism (TFFCA = 1)
With the timer fast flag clear all (TFFCA) enabled, the ECT flags can only be cleared by accessing
the various registers associated with the ECT modes of operation as described below. The flags
cannot be cleared via the normal flag clearing mechanism. This fast flag clearing mechanism has
the advantage of eliminating the software overhead required by a separate clear sequence. Extra
care must be taken to avoid accidental flag clearing due to unintended accesses.
— Input capture
A read from an input capture channel register causes the corresponding channel flag, CxF, to
be cleared in the TFLG1 register.
— Output compare
A write to the output compare channel register causes the corresponding channel flag, CxF, to
be cleared in the TFLG1 register.
— Timer counter
Any access to the TCNT register clears the TOF flag in the TFLG2 register.
— Pulse accumulator A
Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the
PAFLG register.
— Pulse accumulator B
Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.
— Modulus down counter
Any access to the MCCNT register clears the MCZF flag in the MCFLG register.
MC9S12XE-Family Reference Manual , Rev. 1.19
572
Freescale Semiconductor
