S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
7
6
5
4
3
2
1
0
R
AC7
W
Reset
0
0
0
0
0
0
0
0
AC6
AC5
AC4
AC3
AC2
AC1
AC0
7
6
5
4
3
2
1
0
R
AC7
W
Reset
0
0
0
0
0
0
0
0
AC6
AC5
AC4
AC3
AC2
AC1
AC0
7
6
5
4
3
2
1
0
R
AC7
W
Reset
0
0
0
0
0
0
0
0
AC6
AC5
AC4
AC3
AC2
AC1
AC0
7
6
5
4
3
2
1
0
R
AC7
W
Reset
0
0
0
0
0
0
0
0
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Figure 16-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 16-21. CANIDAR0–CANIDAR3 Register Field Descriptions
Field
7:0
AC[7:0]
Description
Acceptance Code Bits
— AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
MC9S12XE-Family Reference Manual , Rev. 1.19
626
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Module Base + 0x0010 (CANIDAR0)
0x0011 (CANIDAR1)
0x0012 (CANIDAR2)
0x0013 (CANIDAR3)