S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
Address
0x0024
0x0026
0x0028
0x002A
0x002C
0x002E
Name
ATDDR10
ATDDR11
ATDDR12
ATDDR13
ATDDR14
ATDDR15
R
W
R
W
R
W
R
W
R
W
R
W
Bit 7
See
and
See
and
See
and
See
and
See
and
= Unimplemented or Reserved
Figure 13-2. ADC12B16C Register Summary (Sheet 3 of 3)
13.3.2
Register Descriptions
This section describes in address order all the ADC12B16C registers and their individual bits.
13.3.2.1
ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence.
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
W
Reset
Reserved
0
0
0
0
0
0
0
WRAP3
1
WRAP2
1
WRAP1
1
WRAP0
1
= Unimplemented or Reserved
Figure 13-3. ATD Control Register 0 (ATDCTL0)
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
Table 13-2. ATDCTL0 Field Descriptions
Field
Description
3-0
WRAP[3-0]
Wrap Around Channel Select Bits
— These bits determine the channel for wrap around when doing multi-
channel conversions. The coding is summarized in
Table 13-3.
Table 13-3. Multi-Channel Wrap Around Coding
WRAP3 WRAP2 WRAP1 WRAP0
0
0
0
0
Multiple Channel Conversions (MULT = 1)
Wraparound to AN0 after Converting
Reserved
(1)
MC9S12XE-Family Reference Manual , Rev. 1.19
506
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
6
5
4
3
2
1
See
Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and
Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
Bit 0
