S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 4 Memory Protection Unit (S12XMPUV1)
4.4
Functional Description
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
The MPU module provides memory protection for accesses coming from multiple masters in the system.
This is done by monitoring bus traffic of each master and compare this with the configuration information
from a set of eight programmable descriptors located in the MPU module. If the MPU module detects an
access violation caused by the S12X CPU, it will assert the CPU access violation interrupt signal. If the
MPU module detects an access violation caused by a bus master other than the S12X CPU, it raises an
access error signal. Please refer to the documentation chapter of the individual master modules (i.e.
XGATE, etc.) for more information about the access error condition.
Violating accesses are not executed. The return value of a violating read access is undefined for both 8 bit
and 16 bit accesses.
NOTE
Accesses from BDM are not restricted. BDM hardware accesses always
bypass the MPU module. During execution of BDM firmware code S12X
CPU accesses are masked from the MPU module as well.
4.4.1
Protection Descriptors
Each of the eight protection descriptors can be used to restrict the allowed types of memory accesses for
a given memory range. Each of these memory ranges can cover up the entire 23 bits global memory range
(8 MBytes).
The descriptors are banked in the MPU module register map.
Each descriptor can be selected for modifying using the SEL bits in the MPU Descriptor Select (MPUSEL)
register.
Table 4-14
gives an overview of the types of accesses that can be configured using the protection
descriptors.
Table 4-14. Access Types
WP
0
0
1
1
NEX
0
1
0
1
Meaning
read, write and execute
read, write
read and execute
read only
The granularity of each descriptor is 8 bytes. This means the protection comparators in the MPU module
cover only address bits [22:3] of each access. The lower address bits [2:0] are ignored.
NOTE
A mis-aligned word access to the upper boundary address of a descriptor is
always flagged as an access violation.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
237
