S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 22 Timer Module (TIM16B8CV2) Block Description
22.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Module Base + 0x0020
7
6
5
4
3
2
1
0
R
W
Reset
0
PAEN
0
0
PAMOD
0
PEDGE
0
CLK1
0
CLK0
0
PAOVI
0
PAI
0
Unimplemented or Reserved
Figure 22-24. 16-Bit Pulse Accumulator Control Register (PACTL)
When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7.
Read: Any time
Write: Any time
Table 22-17. PACTL Field Descriptions
Field
6
PAEN
Description
Pulse Accumulator System Enable
— PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
Pulse Accumulator Mode
— This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table 22-18.
0 Event counter mode.
Pulse Accumulator Edge Control
— This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See
Table 22-18.
0 Falling edges on IOC7 pin cause the count to be incremented.
1 Rising edges on IOC7 pin cause the count to be incremented.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
edge on IOC7 sets the PAIF flag.
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
on IOC7 sets the PAIF flag.
Clock Select Bits —
Refer to
Table 22-19.
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
5
PAMOD
4
PEDGE
3:2
CLK[1:0]
1
PAOVI
0
PAI
MC9S12XE-Family Reference Manual , Rev. 1.19
804
Freescale Semiconductor
