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S912XEG128J2VAL

S912XEG128J2VAL

Model S912XEG128J2VAL
Description IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC
PDF file Total 1327 pages (File size: 7M)
Chip Manufacturer ROCHESTER
Chapter 2 Port Integration Module (S12XEP100PIMV1)
Table 2-51. DDRH Register Field Descriptions (continued)
Field
1
DDRH
Description
Port H data direction—
This register controls the data direction of pin 1.
The enabled SCI6 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 0.
The enabled SCI6 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
0
DDRH
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTH or PTIH registers, when changing the
DDRH register.
2.3.56
Port H Reduced Drive Register (RDRH)
Access: User read/write
(1)
6
5
4
3
2
1
0
Address 0x0263
7
R
RDRH7
W
Reset
0
0
0
0
0
0
0
0
RDRH6
RDRH5
RDRH4
RDRH3
RDRH2
RDRH1
RDRH0
Figure 2-54. Port H Reduced Drive Register (RDRH)
1. Read: Anytime.
Write: Anytime.
Table 2-52. RDRH Register Field Descriptions
Field
7-0
RDRH
Description
Port H reduced drive—Select
reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
MC9S12XE-Family Reference Manual , Rev. 1.19
146
Freescale Semiconductor
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