S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 10 XGATE (S12XGATEV3)
Operation
n
C
RD
0
0
0
n
bits
0
n
= RS or IMM4
Shifts the bits in register RD
n
positions to the left. The lower
n
bits of the register RD become filled with
zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for
n
> 0.
n
can range from 0 to 16.
In immediate address mode,
n
is determined by the operand IMM4.
n
is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode,
n
is determined by the content of RS.
n
is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
N
Z
V
C
∆
N:
Z:
V:
C:
∆
∆
∆
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
old
^ RD[15]
new
Set if
n
> 0 and RD[16-n] = 1; if n = 0 unaffected.
Code and CPU Cycles
Source Form
LSL RD, #IMM4
LSL RD, RS
Address
Mode
IMM4
DYA
0
0
0
0
0
0
0
0
1
1
Machine Code
RD
RD
IMM4
RS
1
1
0
1
1
0
0
0
0
Cycles
P
P
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
433
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
LSL
Logical Shift Left
LSL