S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 10 XGATE (S12XGATEV3)
Operation
~(RS1 ^ RS2)
⇒
RD
~(RD ^ IMM16)⇒ RD
(translates to XNOR RD, #IMM16{15:8]; XNOR RD, #IMM16[7:0])
Performs a bit wise logical exclusive NOR between two 16 bit values and stores the result in the destination
register RD.
Remark: Using R0 as a source registers will calculate the one’s complement of the other source register.
Using R0 as both source operands will fill RD with $FFFF.
NOTE
When using immediate addressing mode (XNOR RD, #IMM16), the Z-flag
of the first instruction (XNORL RD, #IMM16[7:0]) is not considered by the
second instruction (XNORH RD, #IMM16[15:8]).
⇒
Don’t rely on the Z-Flag.
CCR Effects
N
Z
V
C
∆
N:
Z:
V:
C:
∆
0
—
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Refer to XNORH instruction for #IMM16 operations.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
XNOR RD, RS1, RS2
XNOR RD, #IMM16
Address
Mode
TRI
IMM8
IMM8
0
1
1
0
0
0
0
1
1
1
1
1
0
0
1
Machine Code
RD
RD
RD
RS1
RS2
IMM16[7:0]
IMM16[15:8]
1
1
Cycles
P
P
P
MC9S12XE-Family Reference Manual , Rev. 1.19
456
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
XNOR
Logical Exclusive NOR
XNOR