S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 21 Serial Peripheral Interface (S12SPIV5)
Table 21-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
SPPR2
1
1
1
1
1
1
1
1
1
1
SPPR1
1
1
1
1
1
1
1
1
1
1
SPPR0
0
0
1
1
1
1
1
1
1
1
SPR2
1
1
0
0
0
0
1
1
1
1
SPR1
1
1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
0
1
Baud Rate
Divisor
896
1792
16
32
64
128
256
512
1024
2048
Baud Rate
27.90 kbit/s
13.95 kbit/s
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
97.66 kbit/s
48.83 kbit/s
24.41 kbit/s
12.21 kbit/s
21.3.2.4
SPI Status Register (SPISR)
7
6
5
4
3
2
1
0
Module Base +0x0003
R
W
Reset
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
SPIF
0
SPTEF
MODF
0
0
0
0
Figure 21-6. SPI Status Register (SPISR)
Read: Anytime
Write: Has no effect
Table 21-8. SPISR Field Descriptions
Field
7
SPIF
Description
SPIF Interrupt Flag
— This bit is set after received data has been transferred into the SPI data register. For
information about clearing SPIF Flag, please refer to
Table 21-9.
0 Transfer not yet complete.
1 New data copied to SPIDR.
SPI Transmit Empty Interrupt Flag
— If set, this bit indicates that the transmit data register is empty. For
information about clearing this bit and placing data into the transmit data register, please refer to
Table 21-10.
0 SPI data register not empty.
1 SPI data register empty.
Mode Fault Flag
— This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 21.3.2.2, “SPI Control Register 2 (SPICR2)”.
The flag is cleared automatically by a read of the SPI status
register (with MODF set) followed by a write to the SPI control register 1.
1 Mode fault has occurred.
5
SPTEF
4
MODF
MC9S12XE-Family Reference Manual , Rev. 1.19
770
Freescale Semiconductor
