S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 21 Serial Peripheral Interface (S12SPIV5)
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
1
2
3
4
Begin
5
6
7
8
9
10
11
12
13
Transfer
14
15
16
17
18
19
20
21
22
23
24
End
25
26
27
28
29
30
31
32
Begin of Idle State
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
t
T
t
I
t
L
MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
Minimum 1/2 SCK
MSB first (LSBFE = 0)
LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14 MSB
for t
T
, t
l
, t
L
LSB first (LSBFE = 1)
t
L
= Minimum leading time before the first SCK edge, not required for back-to-back transfers
t
T
= Minimum trailing time after the last SCK edge
t
I
= Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
t
L
Figure 21-15. SPI Clock Format 1 (CPHA = 1), with 16-Bit Transfer Width selected (XFRW = 1)
The SS line can remain active low between successive transfers (can be tied low at all times). This format
is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data
line.
• Back-to-back transfers in master mode
In master mode, if a transmission has completed and new data is available in the SPI data register,
this data is sent out immediately without a trailing and minimum idle time.
The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one
half SCK cycle after the last SCK edge.
21.4.4
SPI Baud Rate Generation
Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2,
SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in
the SPI baud rate.
The SPI clock rate is determined by the product of the value in the baud rate preselection bits
(SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor
equation is shown in
Equation 21-3.
BaudRateDivisor = (SPPR + 1)
•
2
(SPR + 1)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
781
If next transfer begins here
SAMPLE I
MOSI/MISO
Eqn. 21-3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
