S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
R5
10.8.2.3
TFR
Register – Register Transfers
R3,CCR
; transfers the condition code register to the low byte of
; register R3
This group comprises transfers from and to some special registers
Branch Instructions
The branch offset is +255 words or -256 words counted from the beginning of the next instruction. Since
instructions have a fixed 16 bit width, the branch offsets are word aligned by shifting the offset value by 2.
BEQ
label
; if Z flag = 1 branch to label
An unconditional branch allows a +511 words or -512 words branch distance.
BRA
label
10.8.2.4
Shift Instructions
Shift operations allow the use of a 4 bit wide immediate value to identify a shift width within a 16 bit word.
For shift operations a value of 0 does not shift at all, while a value of 15 shifts the register RD by 15 bits.
In a second form the shift value is contained in the bits 3:0 of the register RS.
Examples:
LSL
LSR
ASR
R4,#1
R4,#3
R4,R2
; R4 = R4 << 1; shift register R4 by 1 bit to the left
; R4 = R4 >> 3; shift register R4 by 3 bits to the right
; R4 = R4 >> R2;arithmetic shift register R4 right by the amount
;
of bits contained in R2[3:0].
MC9S12XE-Family Reference Manual , Rev. 1.19
384
Freescale Semiconductor