S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
Table 18-2. PITCFLMT Field Descriptions
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Field
7
PITE
Description
PIT Module Enable Bit
— This bit enables the PIT module. If PITE is cleared, the PIT module is disabled and
flag bits in the PITTF register are cleared. When PITE is set, individually enabled timers (PCE set) start down-
counting with the corresponding load register values.
0 PIT disabled (lower power consumption).
1 PIT is enabled.
PIT Stop in Wait Mode Bit
— This bit is used for power conservation while in wait mode.
0 PIT operates normally in wait mode
1 PIT clock generation stops and freezes the PIT module when in wait mode
PIT Counter Freeze while in Freeze Mode Bit
— When during debugging a breakpoint (freeze mode) is
encountered it is useful in many cases to freeze the PIT counters to avoid e.g. interrupt generation. The PITFRZ
bit controls the PIT operation while in freeze mode.
0 PIT operates normally in freeze mode
1 PIT counters are stalled when in freeze mode
6
PITSWAI
5
PITFRZ
1:0
PIT Force Load Bits for Micro Timer 1:0
— These bits have only an effect if the corresponding micro timer is
PFLMT[1:0] active and if the PIT module is enabled (PITE set). Writing a one into a PFLMT bit loads the corresponding 8-bit
micro timer load register into the 8-bit micro timer down-counter. Writing a zero has no effect. Reading these bits
will always return zero.
Note:
A micro timer force load affects all timer channels that use the corresponding micro time base.
18.3.0.2
PIT Force Load Timer Register (PITFLT)
7
6
5
4
3
2
1
0
Module Base + 0x0001
R
W
Reset
0
0
0
0
0
0
0
0
0
PFLT3
0
0
PFLT2
0
0
PFLT1
0
0
PFLT0
0
Figure 18-4. PIT Force Load Timer Register (PITFLT)
Read: Anytime
Write: Anytime
Table 18-3. PITFLT Field Descriptions
Field
3:0
PFLT[3:0]
Description
PIT Force Load Bits for Timer 3-0
— These bits have only an effect if the corresponding timer channel (PCE
set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding
16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will
always return zero.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
681
