S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Appendix A Electrical Characteristics
Table A-5. Thermal Package Characteristics (9S12XEP100)
1
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Num
C
Rating
208MAPBGA
1
2
3
4
5
D
D
D
D
D
Thermal resistance 208MAPBGA, single sided PCB
2
Thermal resistance208MAPBGA, double sided PCB
with 2 internal planes
3
Junction to Board 208MAPBGA
2
Junction to Case 208MAPBGA
4
Junction to Package Top 208MAPBGA
5
LQFP144
6
7
8
9
10
D
D
D
D
D
Thermal resistance LQFP144, single sided PCB
3
Thermal resistance LQFP144, double sided PCB
with 2 internal planes
3
Junction to Board LQFP 144
Junction to Case LQFP 144
4
Junction to Package Top LQFP144
5
LQFP112
11
12
13
14
15
D
D
D
D
D
Thermal resistance LQFP112, single sided PCB
3
Thermal resistance LQFP112, double sided PCB
with 2 internal planes
4
Junction to Board LQFP112
Junction to Case LQFP112
4
Junction to Package Top LQFP112
5
QFP80
16
17
18
19
20
1
2
3
4
5
Symbol
Min
Typ
Max
Unit
θ
JA
θ
JA
θ
JB
θ
JC
Ψ
JT
θ
JA
θ
JA
θ
JB
θ
JC
Ψ
JT
θ
JA
θ
JA
θ
JB
θ
JC
Ψ
JT
θ
JA
θ
JA
θ
JB
θ
JC
Ψ
JT
—
—
—
—
—
—
—
—
—
—
53
31
20
9
2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
—
—
—
—
—
—
—
—
—
—
41
32
22
7.4
3
—
—
—
—
—
—
—
—
—
—
43
32
22
7
3
D
D
D
D
D
Thermal resistance QFP 80, single sided PCB
3
Thermal resistance QFP 80, double sided PCB
with 2 internal planes
3
Junction to Board QFP 80
Junction to Case QFP 80
5
Junction to Package Top QFP 80
6
—
—
—
—
—
—
—
—
—
—
45
33
19
11
3
6
The values for thermal resistance are achieved by package simulations for the 9S12XEP100 die.
Measured per JEDEC JESD51-8. Measured on top surface of the board near the package.
Junction to ambient thermal resistance,
θ
JA
was simulated to be equivalent to the JEDEC specification JESD51-2 in a
horizontal configuration in natural convection.
Junction to ambient thermal resistance,
θ
JA
was simulated to be equivalent to the JEDEC specification JESD51-7 in a
horizontal configuration in natural convection.
Junction to case thermal resistance was simulated to be equivalent to the measured values using the cold plate technique with
the cold plate temperature used as the “case” temperature. This basic cold plate measurement technique is described by
MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package
is being used with a heat sink.
Thermal characterization parameter
Ψ
JT
is the “resistance” from junction to reference point thermocouple on top center of the
case as defined in JESD51-2.
Ψ
JT
is a useful value to use to estimate junction temperature in a steady state customer
enviroment.
MC9S12XE-Family Reference Manual , Rev. 1.19
1208
Freescale Semiconductor
