S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 2 Port Integration Module (S12XEP100PIMV1)
2.3.35
Port S Wired-Or Mode Register (WOMS)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Access: User read/write
(1)
6
5
4
3
2
1
0
Address 0x024E
7
R
WOMS7
W
Reset
0
0
0
0
0
0
0
0
WOMS6
WOMS5
WOMS4
WOMS3
WOMS2
WOMS1
WOMS0
Figure 2-33. Port S Wired-Or Mode Register (WOMS)
1. Read: Anytime.
Write: Anytime.
Table 2-32. WOMS Register Field Descriptions
Field
7-0
WOMS
Description
Port S wired-or mode—Enable
wired-or functionality
This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A
logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
2.3.36
PIM Reserved Register
Access: User read
(1)
6
5
4
3
2
1
0
Address 0x024F
7
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1. Read: Always reads 0x00
Write: Unimplemented
u = Unaffected by reset
Figure 2-34. PIM Reserved Register
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
129