S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 2 Port Integration Module (S12XEP100PIMV1)
2.3.67
Read: Anytime.
Port J Interrupt Enable Register (PIEJ)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Access: User read/write
(1)
6
5
4
3
2
1
0
Address 0x026E
7
R
PIEJ7
W
Reset
0
0
0
0
0
0
0
0
PIEJ6
PIEJ5
PIEJ4
PIEJ3
PIEJ2
PIEJ1
PIEJ0
Figure 2-65. Port J Interrupt Enable Register (PIEJ)
1. Read: Anytime.
Write: Anytime.
Table 2-63. PPSP Register Field Descriptions
Field
7-0
PIEJ
Description
Port J interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port J.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
2.3.68
Port J Interrupt Flag Register (PIFJ)
Access: User read/write
(1)
6
5
4
3
2
1
0
Address 0x026F
7
R
PIFJ7
W
Reset
0
0
0
0
0
0
0
0
PIFJ6
PIFJ5
PIFJ4
PIFJ3
PIFJ2
PIFJ1
PIFJ0
Figure 2-66. Port J Interrupt Flag Register (PIFJ)
1. Read: Anytime.
Write: Anytime.
Table 2-64. PPSP Register Field Descriptions
Field
7-0
PIFJ
Description
Port J interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSJ register. To clear this flag, write logic level 1 to the corresponding bit in the PIFJ register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
MC9S12XE-Family Reference Manual , Rev. 1.19
154
Freescale Semiconductor
