S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Write: Anytime.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
All bits reset to zero.
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared. If PAEN
is set, PA3EN and PA2EN have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBCTL is cleared. If PBEN
is set, PA1EN and PA0EN have no effect.
Table 14-25. ICPAR Field Descriptions
Field
3:0
PA[3:0]EN
8-Bit Pulse Accumulator ‘x’ Enable
0 8-Bit Pulse Accumulator is disabled.
1 8-Bit Pulse Accumulator is enabled.
Description
14.3.2.22 Delay Counter Control Register (DLYCT)
Module Base + 0x0029
7
6
5
4
3
2
1
0
R
W
Reset
DLY7
0
DLY6
0
DLY5
0
DLY4
0
DLY3
0
DLY2
0
DLY1
0
DLY0
0
Figure 14-44. Delay Counter Control Register (DLYCT)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-26. DLYCT Field Descriptions
Field
7:0
DLY[7:0]
Description
Delay Counter Select
— When the PRNT bit of TSCR1 register is set to 0, only bits DLY0, DLY1 are used to
calculate the delay.Table
14-27
shows the delay settings in this case.
When the PRNT bit of TSCR1 register is set to 1, all bits are used to set a more precise delay.
Table 14-28
shows
the delay settings in this case. After detection of a valid edge on an input capture pin, the delay counter counts
the pre-selected number of [(dly_cnt + 1)*4]bus clock cycles, then it will generate a pulse on its output if the level
of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to
narrow input pulses.
Delay between two active edges of the input signal period should be longer than the selected counter delay.
Note:
It is recommended to not write to this register while the timer is enabled, that is when TEN is set in register
TSCR1.
Table 14-27. Delay Counter Select when PRNT = 0
DLY1
0
DLY0
0
Delay
Disabled
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
551
