S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 2 Port Integration Module (S12XEP100PIMV1)
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
Table 2-16. ECLKCTL Register Field Descriptions
Field
7
NECLK
Description
No ECLK—Disable
ECLK output
This bit controls the availability of a free-running clock on the ECLK pin.
Clock output is always active in emulation modes and if enabled in all other operating modes.
1 ECLK disabled
0 ECLK enabled
No ECLKX2—Disable
ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal Bus Clock.
Clock output is always active in emulation modes and if enabled in all other operating modes.
1 ECLKX2 disabled
0 ECLKX2 enabled
Free-running ECLK predivider—Divide
by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider—Configure
ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin. Divider is always disabled in emulation
modes and active as programmed in all other operating modes.
00000 ECLK rate = Bus Clock rate
00001 ECLK rate = Bus Clock rate divided by 2
00010 ECLK rate = Bus Clock rate divided by 3, ...
11111 ECLK rate = Bus Clock rate divided by 32
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
6
NCLKX2
5
DIV16
4-0
EDIV
2.3.16
PIM Reserved Register
Access: User read
(1)
6
5
4
3
2
1
0
Address 0x001D (PRR)
7
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-14. PIM Reserved Register
1. Read: Always reads 0x00
Write: Unimplemented
MC9S12XE-Family Reference Manual , Rev. 1.19
118
Freescale Semiconductor
