S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 21 Serial Peripheral Interface (S12SPIV5)
Table 21-9. SPIF Interrupt Flag Clearing Sequence
XFRW Bit
0
1
SPIF Interrupt Flag Clearing Sequence
Read SPISR with SPIF == 1
Read SPISR with SPIF == 1
then
Read SPIDRL
Byte Read SPIDRL
(1)
or
then
Byte Read SPIDRH
(2)
or
Word Read (SPIDRH:SPIDRL)
1. Data in SPIDRH is lost in this case.
2. SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read
of SPIDRL after reading SPISR with SPIF == 1.
Byte Read SPIDRL
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
771
Table 21-10. SPTEF Interrupt Flag Clearing Sequence
XFRW Bit
0
1
SPTEF Interrupt Flag Clearing Sequence
Read SPISR with SPTEF == 1
then
Read SPISR with SPTEF == 1
Write to SPIDRL
(1)
Byte Write to SPIDRL
1(2)
or
then
Byte Write to SPIDRH
1(3)
Byte Write to SPIDRL
1
or
Word Write to (SPIDRH:SPIDRL)
1
1. Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.
2. Data in SPIDRH is undefined in this case.
3. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by
writing to SPIDRL after reading SPISR with SPTEF == 1.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor