S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 20 Serial Communication Interface (S12SCIV5)
Start Bit
RXD
Samples
1
1
1
0
1
1
1
0
0
0
0
0
0
0
LSB
RT Clock
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT11
RT12
RT13
RT14
RT15
RT16
RT1
RT2
RT Clock Count
Reset RT Clock
RT3
Figure 20-22. Start Bit Search Example 1
In
Figure 20-23,
verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the
perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data
recovery is successful.
Perceived Start Bit
Actual Start Bit
RXD
Samples
1
1
1
1
1
0
1
0
0
0
0
0
LSB
RT Clock
RT10
RT11
RT12
RT13
RT14
RT15
RT16
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT1
RT2
RT3
RT4
RT5
RT6
RT Clock Count
Reset RT Clock
RT7
Figure 20-23. Start Bit Search Example 2
MC9S12XE-Family Reference Manual , Rev. 1.19
750
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
In
Figure 20-22
the verification samples RT3 and RT5 determine that the first low detected was noise and
not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag
is not set because the noise occurred before the start bit was found.