S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 22 Timer Module (TIM16B8CV2) Block Description
Table 22-18. Pin Action
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Pin Action
Falling edge
Rising edge
Div. by 64 clock enabled with pin high level
Div. by 64 clock enabled with pin low level
NOTE
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the
÷64
clock is generated by the timer prescaler.
Table 22-19. Timer Clock Selection
CLK1
0
0
1
1
CLK0
0
1
0
1
Timer Clock
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
For the description of PACLK please refer
Figure 22-24.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
22.3.2.16 Pulse Accumulator Flag Register (PAFLG)
Module Base + 0x0021
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
PAOVF
PAIF
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 22-25. Pulse Accumulator Flag Register (PAFLG)
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags
in the PAFLG register. Timer module must stay enabled (TEN=1) while clearing these bits.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
805
