S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 10 XGATE (S12XGATEV3)
Operation
M[RB, #OFFS5]
M[RB, RI]
M[RB, RI]
RI-2
IMM16
⇒
RD
⇒
RD
⇒
RD;
RI+2
⇒
RI
1
⇒
RI;
M[RS, RI]
⇒
RD
⇒
RD (translates to LDL RD, #IMM16[7:0]; LDH RD, #IMM16[15:8])
Loads a 16 bit value into the register RD.
CCR Effects
N
Z
V
C
—
N:
Z:
V:
C:
—
—
—
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
LDW RD, (RB, #OFFS5)
LDW RD, (RB, RI)
LDW RD, (RB, RI+)
LDW RD, (RB, -RI)
LDW RD, #IMM16
Address
Mode
IDO5
IDR
IDR+
-IDR
IMM8
IMM8
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
1
Machine Code
RD
RD
RD
RD
RD
RD
RB
RB
RB
RB
OFFS5
RI
RI
RI
IMM16[7:0]
IMM16[15:8]
0
0
1
0
1
0
Cycles
PR
PR
PR
PR
P
P
1. If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not be
incremented after the data move: M[RB, RI]
⇒
RD
MC9S12XE-Family Reference Manual , Rev. 1.19
432
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
LDW
Load Word from Memory
LDW