S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 2 Port Integration Module (S12XEP100PIMV1)
This register configures the re-routing of SCI3, IIC0, CS[3:0] on alternative ports.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Table 2-102. Port F Routing Summary
Module
5
4
PTFRR
3
2
1
0
TXD
SCI3
0
1
x
x
x
x
x
x
x
x
x
x
PM7
PF7
SCL
IIC0
x
x
0
1
x
x
x
x
x
x
x
x
PJ7
PF5
CS
CS3
CS2
CS1
CS0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
0
1
PJ0
PF3
PJ5
PF2
PJ2
PF1
PJ4
PF0
RXD
PM6
PF6
SDA
PJ6
PF4
Related Pins
2.4
2.4.1
Functional Description
General
Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an
output from the external bus interface module or a peripheral module or an input to the external bus
interface module or a peripheral module.
2.4.2
Registers
A set of configuration registers is common to all ports with exceptions in the expanded bus interface and
ATD ports (Table
2-103).
All registers can be written at any time, however a specific configuration might
not become active.
Example 2-1. Selecting a pull-up device
This device does not become active while the port is used as a push-pull output.
MC9S12XE-Family Reference Manual , Rev. 1.19
178
Freescale Semiconductor