S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 2 Port Integration Module (S12XEP100PIMV1)
1. Read: Anytime.
Write:Never, writes to this register have no effect.
Table 2-34. PTIM Register Field Descriptions
Field
7-0
PTIM
Description
Port M input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.39
Port M Data Direction Register (DDRM)
Access: User read/write
(1)
6
5
4
3
2
1
0
Address 0x0252
7
R
DDRM7
W
Reset
0
0
0
0
0
0
0
0
DDRM6
DDRM5
DDRM4
DDRM3
DDRM2
DDRM1
DDRM0
Figure 2-37. Port M Data Direction Register (DDRM)
1. Read: Anytime.
Write: Anytime.
Table 2-35. DDRM Register Field Descriptions
Field
7
DDRM
Description
Port M data direction—
This register controls the data direction of pin 7.
The enabled CAN3, routed CAN4, or routed SCI3 forces the I/O state to be an output. In those cases the data
direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated
peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 6.
The enabled CAN3, routed CAN4, or routed SCI3 forces the I/O state to be an input. In those cases the data direction
bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 5.
The enabled CAN2, routed CAN0, or routed CAN4 forces the I/O state to be an output. Depending on the
configuration of the enabled routed SPI0 this pin will be forced to be input or output. In those cases the data direction
bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
6
DDRM
5
DDRM
MC9S12XE-Family Reference Manual , Rev. 1.19
132
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
