S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.3.2.9
Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Module Base + 0x000A
7
6
5
4
3
2
1
0
R
W
Reset
EDG7B
0
EDG7A
0
EDG6B
0
EDG6A
0
EDG5B
0
EDG5A
0
EDG4B
0
EDG4A
0
Figure 14-13. Timer Control Register 3 (TCTL3)
Module Base + 0x000B
7
6
5
4
3
2
1
0
R
W
Reset
EDG3B
0
EDG3A
0
EDG2B
0
EDG2A
0
EDG1B
0
EDG1A
0
EDG0B
0
EDG0A
0
Figure 14-14. Timer Control Register 4 (TCTL4)
Read or write: Anytime
All bits reset to zero.
Table 14-11. TCTL3/TCTL4 Field Descriptions
Field
EDG[7:0]B
7, 5, 3, 1
EDG[7:0]A
6, 4, 2, 0
Description
Input Capture Edge Control
— These eight pairs of control bits configure the input capture edge detector
circuits for each input capture channel. The four pairs of control bits in TCTL4 also configure the input capture
edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the
active edge for the 16-bit pulse accumulator PACB. See
Table 14-12.
Table 14-12. Edge Detector Circuit Configuration
EDGxB
0
0
1
1
EDGxA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
14.3.2.10 Timer Interrupt Enable Register (TIE)
Module Base + 0x000C
7
6
5
4
3
2
1
0
R
W
Reset
C7I
0
C6I
0
C5I
0
C4I
0
C3I
0
C2I
0
C1I
0
C0I
0
Figure 14-15. Timer Interrupt Enable Register (TIE)
MC9S12XE-Family Reference Manual , Rev. 1.19
538
Freescale Semiconductor
