S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Module Base + 0x0014 (CANIDMR0)
0x0015 (CANIDMR1)
0x0016 (CANIDMR2)
0x0017 (CANIDMR3)
7
6
5
4
3
2
1
0
R
AM7
W
Reset
0
0
0
0
0
0
0
0
AM6
AM5
AM4
AM3
AM2
AM1
AM0
7
6
5
4
3
2
1
0
R
AM7
W
Reset
0
0
0
0
0
0
0
0
AM6
AM5
AM4
AM3
AM2
AM1
AM0
7
6
5
4
3
2
1
0
R
AM7
W
Reset
0
0
0
0
0
0
0
0
AM6
AM5
AM4
AM3
AM2
AM1
AM0
7
6
5
4
3
2
1
0
R
AM7
W
Reset
0
0
0
0
0
0
0
0
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Figure 16-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 16-23. CANIDMR0–CANIDMR3 Register Field Descriptions
Field
7:0
AM[7:0]
Description
Acceptance Mask Bits
— If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
MC9S12XE-Family Reference Manual , Rev. 1.19
628
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
