S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2)
28.3.2.5
Flash Configuration Register (FCNFG)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
Offset Module Base + 0x0004
7
6
5
4
3
2
1
0
R
CCIE
W
Reset
0
0
0
IGNSF
0
0
FDFD
FSFD
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 28-9. Flash Configuration Register (FCNFG)
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Table 28-15. FCNFG Field Descriptions
Field
7
CCIE
Description
Command Complete Interrupt Enable
— The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see
Section 28.3.2.7)
Ignore Single Bit Fault
— The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section 28.3.2.8).
0 All single bit faults detected during array reads are reported
generated
Force Double Bit Fault Detect
— The FDFD bit allows the user to simulate a double bit fault during Flash array
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The
FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual
double bit fault is detected.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Section 28.3.2.7)
and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
register is set (see
Section 28.3.2.6)
—
The FSFD bit allows the user to simulate a single bit fault during Flash array
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The
FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single
bit fault is detected.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see
Section 28.3.2.7)
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section 28.3.2.6)
4
IGNSF
1
FDFD
0
FSFD
28.3.2.6
Flash Error Configuration Register (FERCNFG)
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
1093
