S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 8 S12X Debug (S12XDBGV3) Module
•
8.1.4
Modes of Operation
The S12XDBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU12X monitoring is disabled.
Thus breakpoints, comparators, and CPU12X bus tracing are disabled but XGATE bus monitoring
accessing the S12XDBG registers, including comparator registers, is still possible. While in active BDM
or during hardware BDM accesses, XGATE activity can still be compared, traced and can be used to
generate a breakpoint to the XGATE module. When the CPU12X enters active BDM Mode through a
BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed.
The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be
generated if the MCU is secure.
Table 8-3. Mode Dependent Restriction Summary
BDM
Enable
x
0
0
1
1
BDM
Active
x
0
1
0
1
MCU
Secure
1
0
0
0
0
Yes
XGATE only
Comparator
Matches Enabled
Yes
Yes
Breakpoints
Possible
Yes
Only SWI
Yes
XGATE only
Tagging
Possible
Yes
Yes
Yes
XGATE only
Tracing
Possible
No
Yes
Yes
XGATE only
Active BDM not possible when not enabled
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
305
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
•
•
•
•
External CPU12X instruction tagging trigger independent of comparators
XGATE S/W breakpoint request trigger independent of comparators
TRIG Immediate software trigger independent of comparators
Four trace modes
— Normal: change of flow (COF) PC information is stored (see
Section 8.4.5.2.1)
for change of
flow definition.
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Pure PC: All program counter addresses are stored.
4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin, End, and Mid alignment of tracing to trigger
