S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 10 XGATE (S12XGATEV3)
10.2
External Signal Description
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
The XGATE module has no external pins.
10.3
Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the XGATE module.
The memory map for the XGATE module is given below in
Figure 10-2.The
address listed for each register
is the sum of a base address and an address offset. The base address is defined at the SoC level and the
address offset is defined at the module level. Reserved registers read zero. Write accesses to the reserved
registers have no effect.
10.3.1
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bits and field functions follow the register
diagrams, in bit order.
Register
Name
0x0000 R
XGMCTL
15
0
14
0
13
0
12
0
11
0
10
0
9
0
XG
SWEFM
8
0
7
6
5
4
3
2
0
1
0
XG
XG
XG
XGEM
XGSSM
W
FRZM DBGM
FACTM
XG
XGE XGFRZ XGDBG XGSS
FACT
XGIEM
0
XG
XGIE
SWEF
0x0002 R
XGCHID W
0x0003 R
XGCHPL W
0x0004 R
Reserved W
0x0005 R
XGISPSEL W
0x0006 R
XGISP74 W
0x0006 R
XGISP31 W
0x0006
XGVBR
R
W
= Unimplemented or Reserved
XGCHID[6:0]
0
0
0
0
0
XGCHPL[2:0]
0
0
0
0
0
0
XGISPSEL[1:0]
0
0
0
XGISP74[15:1]
XGISP31[15:1]
XGVBR[15:1]
Figure 10-2. XGATE Register Summary (Sheet 1 of 3)
MC9S12XE-Family Reference Manual , Rev. 1.19
354
Freescale Semiconductor
