S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 3 Memory Mapping Control (S12XMMCV4)
Table 3-14. RPAGE Field Descriptions
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Field
7–0
RP[7:0]
Description
RAM Page Index Bits 7–0
— These page index bits are used to select which of the 256 RAM array pages is to
be accessed in the RAM Page Window.
The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and
0x3FFF out of reset.
The fixed 4K page from 0x2000–0x2FFF of RAM is equivalent to page 254 (page number 0xFE).
The fixed 4K page from 0x3000–0x3FFF of RAM is equivalent to page 255 (page number 0xFF).
3.3.2.8
EEPROM Page Index Register (EPAGE)
Address: 0x0017
7
6
5
4
3
2
1
0
R
W
Reset
EP7
1
EP6
1
EP5
1
EP4
1
EP3
1
EP2
1
EP1
1
EP0
0
Figure 3-15. EEPROM Page Index Register (EPAGE)
Read: Anytime
Write: Anytime
These eight index bits are used to page 1 KByte blocks into the EEPROM page window located in the local
(CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see
Figure 3-16).
This supports
accessing up to 256 KByte of EEPROM (in the Global map) within the 64 KByte Local map. The
EEPROM page index register is effectively used to construct paged EEPROM addresses in the Local map
format.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
203
