S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 2 Port Integration Module (S12XEP100PIMV1)
Port
L
Pin Name
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
Pin Function
& Priority
(1)
(TXD7)
GPIO
(RXD7)
GPIO
(TXD6)
GPIO
(RXD6)
GPIO
(TXD5)
GPIO
(RXD5)
GPIO
(TXD4)
GPIO
(RXD4)
GPIO
(TXD3)
GPIO
(RXD3)
GPIO
(SCL0)
GPIO
(SDA0)
GPIO
(CS3)
GPIO
(CS2)
GPIO
(CS1)
GPIO
(CS0)
I/O
O
I
O
I
O
I
O
I
O
I
O
Description
Serial Communication Interface 7 transmit pin
Serial Communication Interface 7 receive pin
Serial Communication Interface 6 transmit pin
Serial Communication Interface 6 receive pin
Serial Communication Interface 5 transmit pin
Serial Communication Interface 5 receive pin
Serial Communication Interface 4 transmit pin
Serial Communication Interface 4 receive pin
Serial Communication Interface 3 transmit pin
Serial Communication Interface 3 receive pin
Inter Integrated Circuit 0 serial clock line
Pin Function
after Reset
GPIO
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
GPIO
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O Inter Integrated Circuit 0 serial data line
I/O General-purpose I/O
O
O
O
O
Chip select 3
Chip select 2
Chip select 1
Chip select 0
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
F
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
GPIO
I/O General-purpose I/O
1. Signals in brackets denote alternative module routing pins.
2. Function active when RESET asserted.
3. Only available in emulation modes or in Special Test Mode with IVIS on.
4. Refer to S12X_EBI section.
2.3
Memory Map and Register Definition
This section provides a detailed description of all Port Integration Module registers.
MC9S12XE-Family Reference Manual , Rev. 1.19
98
Freescale Semiconductor
