S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 5 External Bus Interface (S12XEBIV4)
External bus is available as programmed in normal expanded mode and always full-sized in emulation
modes and special test mode; function not available in single-chip modes.
Table 5-3. EBICTL0 Field Descriptions
Field
7
ITHRS
Description
Reduced Input Threshold
— This bit selects reduced input threshold on external data bus pins and specific
control input signals which are in use with the external bus interface in order to adapt to external devices with a
3.3 V, 5 V tolerant I/O.
The reduced input threshold level takes effect depending on ITHRS, the operating mode and the related enable
signals of the EBI pin function as summarized in
Table 5-4.
0 Input threshold is at standard level on all pins
1 Reduced input threshold level enabled on pins in use with the external bus interface
High Data Byte Enable
— This bit enables the higher half of the 16-bit data bus. If disabled, only the lower 8-
bit data bus can be used with the external bus interface. In this case the unused data pins and the data select
signals (UDS and LDS) are free to be used for alternative functions.
0 DATA[15:8], UDS, and LDS disabled
1 DATA[15:8], UDS, and LDS enabled
External Address Bus Size
— These bits allow scalability of the external address bus. The programmed value
corresponds to the number of available low-aligned address lines (refer to
Table 5-5).
All address lines
ADDR[22:0] start up as outputs after reset in expanded modes. This needs to be taken into consideration when
using alternative functions on relevant pins in applications which utilize a reduced external address bus.
5
HDBE
4–0
ASIZ[4:0]
Table 5-4. Input Threshold Levels on External Signals
ITHRS
External Signal
DATA[15:8]
TAGHI, TAGLO
0
DATA[7:0]
EWAIT
DATA[15:8]
TAGHI, TAGLO
1
DATA[7:0]
Standard
Standard
Reduced
if HDBE = 1
Reduced
Standard
Standard
Standard
NS
SS
NX
ES
Reduced
Standard
Reduced
EX
Reduced
Standard
Reduced
Reduced
ST
Standard
Reduced
Reduced
if EWAIT
if EWAIT
Standard
EWAIT
Standard
(1)
1
enabled
enabled
1. EWAIT function is enabled if at least one CSx line is configured respectively in MMCCTL0. Refer to S12X_MMC section and
Table 5-6.
Table 5-5. External Address Bus Size
ASIZ[4:0]
00000
00001
00010
Available External Address Lines
None
UDS
ADDR1, UDS
MC9S12XE-Family Reference Manual , Rev. 1.19
246
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
This register controls input pin threshold level and determines the external address and data bus sizes in
normal expanded mode. If not in use with the external bus interface, the related pins can be used for
alternative functions.
