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S912XEG128J2VAL

S912XEG128J2VAL

Model S912XEG128J2VAL
Description IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC
PDF file Total 1327 pages (File size: 7M)
Chip Manufacturer ROCHESTER
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Writing to this register when in special modes can alter the MSCAN
functionality.
16.3.2.16 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
Module Base + 0x000F
7
6
5
4
3
2
1
0
R
W
Reset:
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-19. MSCAN Transmit Error Counter (CANTXERR)
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
Write: Unimplemented
NOTE
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
16.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
Section 16.3.3.1,
“Identifier Registers (IDR0–IDR3)”)
of incoming messages in a bit by bit manner (see
Section 16.4.3,
“Identifier Acceptance Filter”).
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
625
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
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