S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 2 Port Integration Module (S12XEP100PIMV1)
Table 2-57. PTJ Register Field Descriptions (continued)
Field
1
PTJ
Description
Port J general purpose input/output data—Data
Register
This pin is associated with the TXD signal of SCI2.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port J general purpose input/output data—Data
Register
This pin is associated with the TXD signal of SCI2 and chip select output CS3. The SCI function takes precedence
over the chip select and general purpose I/O function if the SCI2 is enabled. The chip select takes precedence over
the general purpose I/O.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
0
PTJ
2.3.62
Port J Input Register (PTIJ)
Access: User read
(1)
6
5
4
3
2
1
0
Address 0x0269
7
R
W
Reset
PTIJ7
PTIJ6
PTIJ5
PTIJ4
PTIJ3
PTIJ2
PTIJ1
PTIJ0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
1. Read: Anytime.
Write:Never, writes to this register have no effect.
u = Unaffected by reset
Figure 2-60. Port J Input Register (PTIJ)
Table 2-58. PTIJ Register Field Descriptions
Field
7-0
PTIJ
Description
Port J input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.63
Port J Data Direction Register (DDRJ)
Access: User read/write
(1)
6
5
4
3
2
1
0
Address 0x026A
7
R
DDRJ7
W
Reset
0
0
0
0
0
0
0
0
DDRJ6
DDRJ5
DDRJ4
DDRJ3
DDRJ2
DDRJ1
DDRJ0
Figure 2-61. Port J Data Direction Register (DDRJ)
MC9S12XE-Family Reference Manual , Rev. 1.19
150
Freescale Semiconductor
