S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
Read: Anytime
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Write: Anytime (causes the scale counter to load the PWMSCLB value).
19.3.2.11 Reserved Registers (PWMSCNTx)
The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are
not available in normal modes.
Module Base + 0x000A, 0x000B
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-13. Reserved Registers (PWMSCNTx)
Read: Always read $00 in normal modes
Write: Unimplemented in normal modes
NOTE
Writing to these registers when in special modes can alter the PWM
functionality.
19.3.2.12 PWM Channel Counter Registers (PWMCNTx)
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source.
The counter can be read at any time without affecting the count or the operation of the PWM channel. In
left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned
output mode, the counter counts from 0 up to the value in the period register and then back down to 0.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,
the immediate load of both duty and period registers with values from the buffers, and the output to change
according to the polarity bit. The counter is also cleared at the end of the effective period (see
Section 19.4.2.5, “Left Aligned Outputs”
and
Section 19.4.2.6, “Center Aligned Outputs”
for more
details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a
PWMCNTx register. For more detailed information on the operation of the counters, see
Section 19.4.2.4,
“PWM Timer Counters”.
high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
705
