• Inventory
  • Products
  • Technical Information
  • Circuit Diagram
  • Data Sheet
Data Sheet
Home > Data Sheet > S912XEG128J2VAL
S912XEG128J2VAL

S912XEG128J2VAL

Model S912XEG128J2VAL
Description IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC
PDF file Total 1327 pages (File size: 7M)
Chip Manufacturer ROCHESTER
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
19.2.1
PWM7 — PWM Channel 7
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
This pin serves as waveform output of PWM channel 7 and as an input for the emergency shutdown
feature.
19.2.2
PWM6 — PWM Channel 6
This pin serves as waveform output of PWM channel 6.
19.2.3
PWM5 — PWM Channel 5
This pin serves as waveform output of PWM channel 5.
19.2.4
PWM4 — PWM Channel 4
This pin serves as waveform output of PWM channel 4.
19.2.5
PWM3 — PWM Channel 3
This pin serves as waveform output of PWM channel 3.
19.2.6
PWM3 — PWM Channel 2
This pin serves as waveform output of PWM channel 2.
19.2.7
PWM3 — PWM Channel 1
This pin serves as waveform output of PWM channel 1.
19.2.8
PWM3 — PWM Channel 0
This pin serves as waveform output of PWM channel 0.
19.3
Memory Map and Register Definition
This section describes in detail all the registers and register bits in the PWM module.
The special-purpose registers and register bit functions that are not normally available to device end users,
such as factory test control registers and reserved registers, are clearly identified by means of shading the
appropriate portions of address maps and register diagrams. Notes explaining the reasons for restricting
access to the registers and functions are also explained in the individual register descriptions.
19.3.1
Module Memory Map
This section describes the content of the registers in the PWM module. The base address of the PWM
module is determined at the MCU level when the MCU is defined. The register decode map is fixed and
begins at the first address of the module address offset. The figure below shows the registers associated
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
693
Go Upload

* Only PDF files are allowed for upload

* Enter up to 200 characters.