S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 10 XGATE (S12XGATEV3)
Operation
RS
⇒
M[RB, #OFFS5]
RS
⇒
M[RB, RI]
RS
⇒
M[RB, RI];
RI+2
⇒
RI;
RI–2
⇒
RI;
RS
⇒
M[RB, RI]
1
Stores the content of register RS to memory.
CCR Effects
N
Z
V
C
—
N:
Z:
V:
C:
—
—
—
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
STW RS, (RB, #OFFS5)
STW RS, (RB, RI)
STW RS, (RB, RI+)
STW RS, (RB, -RI)
Address
Mode
IDO5
IDR
IDR+
-IDR
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
Machine Code
RS
RS
RS
RS
RB
RB
RB
RB
OFFS5
RI
RI
RI
0
0
1
0
1
0
Cycles
PW
PW
PW
PW
1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source
register is written to the memory: RS
⇒
M[RB, RS–2]; RS–2
⇒
RS
MC9S12XE-Family Reference Manual , Rev. 1.19
450
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
STW
Store Word to Memory
STW