S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.3.2.8
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Module Base + 0x0008
7
6
5
4
3
2
1
0
R
W
Reset
OM7
0
OL7
0
OM6
0
OL6
0
OM5
0
OL5
0
OM4
0
OL4
0
Figure 14-11. Timer Control Register 1 (TCTL1)
Module Base + 0x0009
7
6
5
4
3
2
1
0
R
W
Reset
OM3
0
OL3
0
OM2
0
OL2
0
OM1
0
OL1
0
OM0
0
OL0
0
Figure 14-12. Timer Control Register 2 (TCTL2)
Read or write: Anytime
All bits reset to zero.
Table 14-9. TCTL1/TCTL2 Field Descriptions
Field
OM[7:0]
7, 5, 3, 1
OL[7:0]
6, 4, 2, 0
Description
OMx — Output Mode
OLx — Output Level
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful
OCx compare. When either OMx or OLx is one, the pin associated with OCx becomes an output tied to OCx.
See
Table 14-10.
Table 14-10. Compare Result Output Action
OMx
0
0
1
1
OLx
0
1
0
1
Action
No output compare
action on the timer output signal
Toggle OCx output line
Clear OCx output line to zero
Set OCx output line to one
NOTE
To enable output action by OMx and OLx bits on timer port, the
corresponding bit in OC7M should be cleared.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
537