S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
Table 17-3. PITFLT Field Descriptions
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Field
7:0
PFLT[7:0]
Description
PIT Force Load Bits for Timer 7-0
— These bits have only an effect if the corresponding timer channel (PCE
set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding
16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will
always return zero.
17.3.0.3
PIT Channel Enable Register (PITCE)
7
6
5
4
3
2
1
0
Module Base + 0x0002
R
W
Reset
PCE7
0
PCE6
0
PCE5
0
PCE4
0
PCE3
0
PCE2
0
PCE1
0
PCE0
0
Figure 17-5. PIT Channel Enable Register (PITCE)
Read: Anytime
Write: Anytime
Table 17-4. PITCE Field Descriptions
Field
7:0
PCE[7:0]
Description
PIT Enable Bits for Timer Channel 7:0
— These bits enable the PIT channels 7-0. If PCE is cleared, the PIT
channel is disabled and the corresponding flag bit in the PITTF register is cleared. When PCE is set, and if the
PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-
counting.
0 The corresponding PIT channel is disabled.
1 The corresponding PIT channel is enabled.
17.3.0.4
PIT Multiplex Register (PITMUX)
7
6
5
4
3
2
1
0
Module Base + 0x0003
R
W
Reset
PMUX7
0
PMUX6
0
PMUX5
0
PMUX4
0
PMUX3
0
PMUX2
0
PMUX1
0
PMUX0
0
Figure 17-6. PIT Multiplex Register (PITMUX)
Read: Anytime
Write: Anytime
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
665
