S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
t
lock
j
1
j
2
f
bus
f
bus
f
bus
Min
1
32
1
0
0.5
—
—
—
—
—
—
Typ
—
—
—
—
—
214
—
—
—
—
—
Max
4
120
40
1.5
2.5
150 +
256/f
REF
1.2
0
48
49
49
Unit
MHz
MHz
MHz
%
2
%
2
µs
%
%
MHz
MHz
MHz
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
P Self Clock Mode frequency
1
C VCO locking range
C Reference Clock
D Lock Detection
D Un-Lock Detection
C Time to lock
C Jitter fit parameter 1
3
C Jitter fit parameter 2
3
D Bus Frequency for FM1=1, FM0=1 (frequency
modulation in PLLCTL register of s12xe_crg)
D Bus Frequency for FM1=1, FM0=0 (frequency
modulation in PLLCTL register of s12xe_crg)
D Bus Frequency for FM1=0, FM0=1 (frequency
modulation in PLLCTL register of s12xe_crg)
1
2
3
Bus frequency is equivalent to f
SCM
/2
% deviation from target frequency
f
OSC
= 4MHz, f
BUS
= 50MHz equivalent f
PLL
= 100MHz: REFDIV=$01, REFRQ=01, SYNDIV=$18, VCOFRQ=11, POSTDIV=$
00.
A.7
A.7.1
External Interface Timing
MSCAN
Table A-26. MSCAN Wake-up Pulse Characteristics
Conditions are shown in
Table A-4
unless otherwise noted
Num C
1
2
Rating
Symbol
t
WUP
t
WUP
Min
—
5
Typ
—
—
Max
1.5
—
Unit
µs
µs
P MSCAN wakeup dominant pulse filtered
P MSCAN wakeup dominant pulse pass
A.7.2
SPI Timing
This section provides electrical parametrics and ratings for the SPI. In
Table A-27
the measurement
conditions are listed.
MC9S12XE-Family Reference Manual , Rev. 1.19
1240
Freescale Semiconductor
