S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 5 External Bus Interface (S12XEBIV4)
Table 5-9. Summary of Functions (continued)
Single-Chip Modes
Properties
(if Enabled)
Flash area
address access
(4)
Normal
Single-Chip
—
Special
Single-Chip
—
Normal
Expanded
—
Signal Properties
Bus signals
—
—
ADDR[22:1]
DATA[15:0]
ADDR[22:20]/
ACC[2:0]
ADDR[19:16]/
IQSTAT[3:0]
ADDR[15:0]/
IVD[15:0]
DATA[15:0]
ADDR0
LSTRB
RW
ADDR[22:20]/
ACC[2:0]
ADDR[19:16]/
IQSTAT[3:0]
ADDR[15:0]/
IVD[15:0]
DATA[15:0]
ADDR0
LSTRB
RW
CS0
CS1
CS2
CS3
EWAIT
ADDR[22:0]
DATA[15:0]
Expanded Modes
Emulation
Single-Chip
1 cycle
Emulation
Expanded
1 cycle
Special
Test
1 cycle
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Data select signals
(if 16-bit data bus)
Data direction signals
—
—
—
—
UDS
LDS
RE
WE
CS0
CS1
CS2
CS3
EWAIT
ADDR0
LSTRB
RW
Chip Selects
—
—
—
—
External wait
feature
—
—
—
—
Reduced input
—
—
Refer to
DATA[15:0]
DATA[15:0]
Refer to
threshold enabled on
Table 5-4
EWAIT
EWAIT
Table 5-4
1. Incl. S12X_EBI registers
2. Refer to S12X_MMC section.
3. If EWAIT enabled for at least one CSx line (refer to S12X_MMC section), the minimum number of external bus cycles is 3.
4. Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section).
5.4.2
Internal Visibility
Internal visibility allows the observation of the internal CPU address and data bus as well as the
determination of the access source and the CPU pipe (queue) status through the external bus interface.
Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal
CPU accesses are made visible on the external bus interface except CPU execution of BDM firmware
instructions.
Internal reads are made visible on ADDRx/IVDx (address and read data multiplexed, see
Table 5-12
to
Table 5-14),
internal writes on ADDRx and DATAx (see
Table 5-15
to
Table 5-17).
RW and LSTRB
show the type of access. External read data are also visible on IVDx.
During ‘no access’ cycles RW is held in read position while LSTRB is undetermined.
All accesses which make use of the external bus interface are considered external accesses.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
249
