S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Module Base + 0xXXXF
7
6
5
4
3
2
1
0
R
W
Reset:
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
x
x
x
x
x
x
x
x
Figure 16-38. Time Stamp Register — Low Byte (TSRL)
Read: Anytime when TXEx flag is set (see
Section 16.3.2.7, “MSCAN Transmitter Flag Register
(CANTFLG)”)
and the corresponding transmit buffer is selected in CANTBSEL (see
Section 16.3.2.11,
“MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
16.4
16.4.1
Functional Description
General
This section provides a complete functional description of the MSCAN. It describes each of the features
and modes listed in the introduction.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
639
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages