S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
Module Base + 0x0002
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
POSTDIV[4:0]
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-5. S12XECRG Post Divider Register (POSTDIV)
Read: Anytime
Write: Anytime except if PLLSEL = 1
f VCO
f PLL
=
-------------------------------------
-
(
2xPOSTDIV
)
NOTE
If POSTDIV = $00 then f
PLL
is identical to f
VCO
(divide by one).
11.3.2.4
S12XECRG Flags Register (CRGFLG)
This register provides S12XECRG status bits and flags.
Module Base + 0x0003
7
6
5
4
3
2
1
0
R
RTIF
W
Reset
0
Note 1
Note 2
Note 3
PORF
LVRF
LOCKIF
LOCK
ILAF
0
0
SCMIF
0
SCM
0
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset.
= Unimplemented or Reserved
Figure 11-6. S12XECRG Flags Register (CRGFLG)
Read: Anytime
Write: Refer to each bit for individual write conditions
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
473