S912XEG128J2VAL
| Model | S912XEG128J2VAL |
| Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
| PDF file | Total 1327 pages (File size: 7M) |
| Chip Manufacturer | ROCHESTER |
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
All bits reset to zero.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
Table 14-18. PACTL Field Descriptions
Field
6
PAEN
Description
Pulse Accumulator A System Enable
— PAEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable
bits in ICPAR are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled.
1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded
to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR have no effect.
Pulse Accumulator Input Edge Flag (PAIF) function is enabled. The PACA shares the input pin with IC7.
Pulse Accumulator Mode
— This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1).
0 Event counter mode
1 Gated time accumulation mode
Pulse Accumulator Edge Control
— This bit is active only when the Pulse Accumulator A is enabled
(PAEN = 1). Refer to
Table 14-19.
For PAMOD bit = 0 (event counter mode).
0 Falling edges on PT7 pin cause the count to be incremented
1 Rising edges on PT7 pin cause the count to be incremented
For PAMOD bit = 1 (gated time accumulation mode).
0 PT7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on PT7
sets the PAIF flag.
1 PT7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on PT7
sets the PAIF flag.
If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64 since the
÷64
clock is generated by the
timer prescaler.
3:2
CLK[1:0]
Clock Select Bits
— For the description of PACLK please refer to
Figure 14-71.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input
clock to the timer counter. The change from one selected clock to the other happens immediately after these bits
are written. Refer to
Table 14-20.
Pulse Accumulator A Overflow Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PAOVF is set
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PAIF is set
5
PAMOD
4
PEDGE
2
PAOVI
0
PAI
.
Table 14-19. Pin Action
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Falling edge
Rising edge
Divide by 64 clock enabled with pin high level
Divide by 64 clock enabled with pin low level
Pin Action
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
545
