S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1)
Offset Module Base + 0x000E
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
ECCR[15:8]
0
0
0
0
= Unimplemented or Reserved
Figure 26-20. Flash ECC Error Results High Register (FECCRHI)
Offset Module Base + 0x000F
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
ECCR[7:0]
0
0
0
0
= Unimplemented or Reserved
Figure 26-21. Flash ECC Error Results Low Register (FECCRLO)
All FECCR bits are readable but not writable.
Table 26-27. FECCR Index Settings
ECCRIX[2:0]
Bits [15:8]
000
001
010
011
100
101
110
111
Parity bits read from
Flash block
FECCR Register Content
Bit[7]
CPU or XGATE
source identity
Global address [15:0]
Data 0 [15:0]
Data 1 [15:0] (P-Flash only)
Data 2 [15:0] (P-Flash only)
Data 3 [15:0] (P-Flash only)
Not used, returns 0x0000 when read
Not used, returns 0x0000 when read
Bits[6:0]
Global address
[22:16]
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
981
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
fault information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults, the priority for fault recording is:
1. Double bit fault over single bit fault
2. CPU over XGATE