S912XEG128J2VAL
Model | S912XEG128J2VAL |
Description | IC,MICROCONTROLLER,16-BIT,CPU12 CPU,CMOS,QFP,112PIN,PLASTIC |
PDF file | Total 1327 pages (File size: 7M) |
Chip Manufacturer | ROCHESTER |
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.2.1
IOC7 — Input Capture and Output Compare Channel 7
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: S12XE products in 208 MAPBGA packages
This pin serves as input capture or output compare for channel 7.
14.2.2
IOC6 — Input Capture and Output Compare Channel 6
This pin serves as input capture or output compare for channel 6.
14.2.3
IOC5 — Input Capture and Output Compare Channel 5
This pin serves as input capture or output compare for channel 5.
14.2.4
IOC4 — Input Capture and Output Compare Channel 4
This pin serves as input capture or output compare for channel 4.
14.2.5
IOC3 — Input Capture and Output Compare Channel 3
This pin serves as input capture or output compare for channel 3.
14.2.6
IOC2 — Input Capture and Output Compare Channel 2
This pin serves as input capture or output compare for channel 2.
14.2.7
IOC1 — Input Capture and Output Compare Channel 1
This pin serves as input capture or output compare for channel 1.
14.2.8
IOC0 — Input Capture and Output Compare Channel 0
NOTE
For the description of interrupts see
Section 14.4.3, “Interrupts”.
This pin serves as input capture or output compare for channel 0.
14.3
Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
14.3.1
Module Memory Map
The memory map for the ECT module is given below in the
Table 14-2.
The address listed for each register
is the address offset. The total address for each register is the sum of the base address for the ECT module
and the address offset for each register.
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
527